1. Field of the Invention
The present invention relates to a display apparatus that synchronizes a synchronous signal and an inverter driving signal in response to a display mode, and a control method thereof.
2. Discussion of the Background
Flat panel displays such as an organic light emitting device (OLED), a plasma display panel (PDP), and a liquid crystal display (LCD) have been actively developed as substitutes for the cathode ray tube (CRT), which may be heavy and large.
A PDP is a device that displays characters or images using plasma generated by a gas-discharge, and an OLED is a device that displays characters or images using electroluminescence of a specific organic material or high molecular weight polymeric compounds. An LCD displays desired images by applying an electric field to a liquid crystal (LC) layer disposed between two panels and regulating the strength of the electric field to adjust the transmittance of light passing through the LC layer.
Among such flat panel displays, the LCD and the OLED may each include a display panel provided with pixels including switching elements and display signal lines, a gate driver for providing gate signals to gate lines among the display signal lines to turn on/off the switching elements of the pixels, a gray voltage generator for generating a plurality of gray voltages, a data driver for selecting a voltage corresponding to image data as a data voltage from the gray voltages and applying the data voltage to a data line among the display signal lines, and a signal controller for controlling the above elements. Each driver may be supplied with necessary predetermined voltages and convert them into various voltages to drive the display device. For example, the gate driver may receive a gate-on voltage and a gate-off voltage and alternately apply them to the gate line as a gate signal, and a gray voltage generator may receive a uniform reference voltage and divide it through a plurality of resistors to provide divided voltages to a data driver.
The LCD includes a liquid crystal to display an image, a backlight unit to emit light to the liquid crystal and an inverter to supply a current to the backlight unit.
A thin film transistor (TFT) LCD includes a plurality of pixels that includes a switching element such as an amorphous silicon (a-si) TFT or poly-crystalline silicon (p-si) TFT and a liquid crystal (LC) capacitor.
An a-Si TFT includes a gate electrode, a drain electrode, a source electrode, and a channel, which includes an a-si layer as a passage of electrical carriers from the source electrode to the drain electrode.
The a-Si used in a TFT LCD is sensitive to light. That is, an a-Si TFT becomes conductive and a resistance is reduced when receiving light. When the light is removed, the a-Si TFT becomes semi-conductive and a resistance rises relatively to be affected by a charging voltage of a liquid crystal capacitor. When light is emitted to the a-Si TFT, an overall parasitic capacity of data lines may be changed and a screen noise may be created.
When the backlight unit emits light consistently, a liquid crystal panel receives light uniformly, which does not trigger any problem. However, a problem may arise when brightness of the backlight unit is adjusted by pulse-width modulation (PWM), which involves turning on and off the backlight unit periodically to improve display quality.
When a frequency ratio of a synchronous signal and a PWM signal do not synchronized, regular movement of lines may be found in each frame, which is called waterfall noise.
Thus, display apparatuses have recently employed a synchronous inverter to synchronize the frequency of the synchronous signal and the PWM frequency, i.e., an inverter driving signal, at a proper ratio that may minimize such a noise. The currently employed synchronization is based on a horizontal synchronous signal Hsync synchronized on the basis of a horizontal line time clock or based on a vertical synchronous signal Vsync synchronized on the basis of a frame time.
The PWM frequency may be synchronized by multiplying a/b by a frequency of the horizontal synchronous signal HSYNC, or the PWM frequency may be synchronized by multiplying c/d by a frequency of the vertical synchronous signal VSYNC The multiplication numbers may be inputted as a numerator and a denominator to be multiplied. The multiplication numbers may be properly determined during a manufacturing stage of the display apparatus.
An LCD displays images of various modes in turn, such as a TV mode and a personal computer (PC) mode. When the LCD displays images of the TV mode, images of a high frame frequency, e.g. 120 Hz, may be required to provide smooth moving pictures to viewers because TV shows rapid movements of objects. When the LCD displays images of the PC mode, images of a low frame frequency, e.g. 60 Hz, may be required, because the PC monitor shows more fixed images than moving images.
When the frame frequency varies according to the display modes, the frequency of the vertical synchronous signal may also vary in response to the frame frequency and may be multiplied by the predetermined multiplication number to make the synchronous waveform to minimize waterfall noise.
However, the frequency of the vertical synchronous signal may abnormally vary for several seconds. The abnormal variation of the frequency of the vertical synchronous signal may result in an undesired PWM signal frequency.